Field
The present disclosure relates to packaged semiconductor devices and printed circuit boards and, more specifically but not exclusively, to the interconnection arrays (e.g., ball grid arrays and their corresponding landing pad arrays) used to mate packaged semiconductor devices to printed circuit boards.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Some conventional packaged semiconductor devices have a ball grid array (BGA), which comprises solder balls arranged in the rows and columns of a two-dimensional, rectangular grid. These packaged devices are designed to mount onto a printed circuit board (PCB) having a landing pad array, which comprises landing pads arranged in the rows and columns of a corresponding two-dimensional, rectangular grid, such that each BGA solder ball of the packaged device mates with a corresponding landing pad in the PCB landing pad array.
Some of the BGA solder balls are power solder balls that provide power supply voltages (including ground) to the semiconductor die of the packaged device, while other BGA solder balls are signal solder balls that transmit signals to and/or from the semiconductor die. These power solder balls and signal solder balls are configured to mate with corresponding power landing pads and signal landing pads, respectively, in the PCB landing pad array.
Conventional printed circuit boards have different layers that function as either signal routing layers or power planes. In plated through-hole technology, each landing pad on the PCB top layer has a metalized via extending from that PCB top layer all the way down to the PCB bottom layer, where the via provides an electrical connection from the landing pad to only one of those PCB layers. The other PCB layers through which the via passes have anti-pads, which are regions devoid of metal to prevent electrical interconnection between the via and those layers. The PCB layer to which the via is electrically connected has one or more metal features (e.g., signal traces or power planes) that provide a conducting path to electrically connect the landing pad to other devices mounted on the PCB or to components external to the PCB.
Each power landing pad has a corresponding via that electrically connects the power landing pad to a PCB layer that functions as a power plane. A given ball grid array and its corresponding landing pad array may have a number of different solder balls and landing pads designed to carry the same power supply voltage level. All landing pads that are associated with the same power supply voltage level are typically connected to the same corresponding power plane.
On the other hand, each signal landing pad has a corresponding via that electrically connects the signal landing pad to a PCB layer that functions as a signal routing layer. Typically, each signal landing pad carries a unique signal that is different from every other signal carried by every other signal landing pad. As such, the PCB signal routing layer that is connected to a signal landing pad must have a unique conducting path (e.g., trace) for the distinct signal associated with that signal landing pad. Each PCB signal routing layer typically has conducting paths or traces for many different signal landing pads. Depending on the particular design, a printed circuit board may have multiple signal routing layers in order to accommodate all of the different, unique signals. In order to keep the number of signal routing layers in the PCB as small as possible (to keep costs down), it is desirable to route as many different signals within each signal routing layer as possible.
Within each PCB signal routing layer, each via constitutes a physical obstruction that can inhibit the ability to route conducting paths for those signals connected to that PCB layer. As packaged devices get smaller and in order to conserve layout area on printed circuit boards, it is desirable to reduce the pitch of the ball grid arrays and corresponding landing pad arrays, where the pitch refers to the distance between the centers of adjacent solder balls or adjacent landing pads. Unfortunately, as the pitch gets smaller, it typically takes more PCB signal routing layers to route signals to and from the different signal landing pads, because there is simply less room between obstructing vias to route those signals.